Custom ASIC Packaging Risk Allocation: Broadcom vs. Alphabet

Alphabet ultimately absorbs the take-or-pay and underutilization risk on TSMC’s CoWoS capacity, not Broadcom.

Broadcom’s corporate model is specifically structured to avoid taking speculative, unhedged balance-sheet exposure on foundry and packaging capacity. The financial and contractual mechanisms governing custom Application-Specific Integrated Circuits (ASICs) like Google’s Tensor Processing Units (TPUs) place the burden of stranded capacity on the hyperscaler commissioning the silicon.

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1. Broadcom’s Disclosures: No Long-Term Minimum Commitments to TSMC

In its Form 10-K for the fiscal year ended November 2, 2025 (Item 1A, Risk Factors), Broadcom details its operational relationship with foundries and advanced packaging providers:

• Heavy Concentration at TSMC: "During fiscal year 2025, approximately 95% of the wafers manufactured by our CMs [contract manufacturers] were produced by TSMC."
• The Refusal to Take Long-Term Foundry Risk: Crucially, Broadcom discloses:

  "We do not generally have long-term capacity commitments with our CMs and substantially all of our manufacturing services are on a purchase order basis with no minimum quantities."

Broadcom does not enter into multi-year, unilateral "take-or-pay" capacity reservations with TSMC on its own account. Unlike a merchant silicon designer that must prepay tens of billions of dollars to guarantee capacity for off-the-shelf catalog products, Broadcom operates its custom ASIC business on a strict, back-to-back purchase-order basis.

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2. How CoWoS Capacity Is Secured for Custom ASICs

Leading-edge packaging lines—specifically Chip-on-Wafer-on-Substrate (CoWoS)—require significant capital expenditure and months of advance commitment. Because Broadcom does not carry take-or-pay obligations on its own books, TSMC’s CoWoS allocation for the TPU program relies on structural backstops provided by Alphabet:

1. Back-to-Back Purchase Orders: When Broadcom places firm orders with TSMC for front-end wafer fabrication and CoWoS packaging, it does so against firm, legally binding purchase commitments from Alphabet. If Alphabet decides to dial back procurement, the commercial contract between Alphabet and Broadcom dictates that Alphabet is liable for all committed components, work-in-process (WIP), dedicated non-fungible materials (such as High-Bandwidth Memory stacks customized for Google's interposers), and supplier cancellation fees.
2. Capital Prepayments and Tooling: TSMC requires customers to justify massive capacity expansions by funding dedicated tooling or providing advance deposits. For hyperscale custom programs, these customer-funded advances originate from the hyperscaler’s balance sheet, ensuring that TSMC is protected if volume fails to materialize.
3. Alphabet’s Multi-Year Purchase Commitments: Alphabet’s balance sheet reflects the absorption of these obligations. Alphabet carries hundreds of billions of dollars in multi-year purchase and infrastructure commitments, which encompass third-party hardware, custom compute pipelines, and dedicated data center energy infrastructure.

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3. Broadcom vs. Merchant GPU Models (NVIDIA)

The division of risk between Broadcom and Alphabet highlights the fundamental structural difference between the custom ASIC model and the merchant accelerator model:

| Risk Parameter | The Merchant Model (NVIDIA) | The Custom ASIC Model (Broadcom / Alphabet) | | :--- | :--- | :--- | | Primary Counterparty to TSMC | NVIDIA Corporation | Broadcom (acting as turnkey design & supply partner) | | Balance-Sheet Capacity Risk | NVIDIA bears 100% of the risk ($279B in supply/capacity obligations, with $92B front-loaded). | Alphabet bears the ultimate capacity risk through firm purchase contracts and customer-funded prepayments. | | Impact of a Demand Freeze | NVIDIA takes multi-billion-dollar write-downs for excess purchase obligations and stranded inventory (as seen in the $4.5B H20 charge in FY26). | Broadcom loses future high-margin development and royalty revenue, but does not take balance-sheet write-offs for idle packaging lines; Alphabet absorbs the committed hardware costs. |

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Investment Verdict

If hyperscaler demand cools and TPU buildouts slow down:

• Broadcom experiences an operational headwind in the form of lower top-line revenue growth in its custom AI semiconductor segment, but its gross margins and balance sheet remain insulated from idle-capacity penalties because it does not carry minimum purchase guarantees with TSMC.
• Alphabet bears the financial pain. It must either take delivery of expensive, pre-committed TPU modules that dilute capital returns on invested capital (ROIC), pay contractual cancellation and rescheduling charges to cover TSMC's unabsorbed cleanroom tooling, or allow dedicated advanced packaging capacity to sit idle while continuing to service committed infrastructure agreements.

If Alphabet bears the balance-sheet capital risk and takes the capacity commitments with TSMC, a natural question arises: Why does Alphabet need Broadcom at all? Why shouldn’t Alphabet deal directly with TSMC as an internal design house, or freely swap Broadcom out for a lower-cost design-services firm like MediaTek or Marvell?

Broadcom’s moat in custom AI accelerators (XPUs) does not rest on balance-sheet risk absorption. Instead, it is anchored in hard intellectual property, physical integration complexity at the packaging frontier, and deep system-level architectural lock-in.

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1. The High-Speed SerDes Monopoly

The primary performance bottleneck in large-scale AI clusters is not raw mathematical compute on the die; it is bandwidth and latency—moving data from die to die, die to High-Bandwidth Memory (HBM), and node to node across hundreds of thousands of accelerators.

• Critical Physical-Layer IP: Broadcom holds the industry’s benchmark portfolio of high-speed Serializer/Deserializer (SerDes) intellectual property. SerDes circuits convert parallel data from compute logic into ultra-fast serial streams running across copper traces, optical engines, and printed circuit boards.
• The Physics Barrier: Moving from 112 Gbps to 224 Gbps—and toward next-generation 448 Gbps and co-packaged optics—pushes the physical limits of signal attenuation, noise, and power consumption. If a SerDes block fails or consumes too much thermal headroom, the entire accelerator cluster stalls.
• Make-vs-Buy Economics: Developing proprietary SerDes that matches Broadcom's bit-error-rate and power-efficiency metrics costs hundreds of millions of dollars in dedicated mixed-signal engineering and takes years of physical silicon verification. Even a hyperscaler with Alphabet’s balance sheet finds it cheaper and far less risky to pay Broadcom a margin spread than to risk cluster-wide interconnect failure on a multi-billion-dollar tape-out.

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2. Physical Packaging and Turnkey Integration Yields

Alphabet designs the logical microarchitecture of the TPU (matrix multiply units, tensor cores, and memory layouts), but turning a digital logic design into a working, high-yielding multi-die physical package is an entirely different discipline.

In Item 1 of its Form 10-K for the fiscal year ended November 2, 2025, Broadcom outlines what its custom silicon platform actually does:

"Our custom silicon solutions provide the platform to integrate embedded logic, high-bandwidth memory, serializer/deserializer technology, IP cores and processor cores using advanced packaging technologies. ASICs are custom products built to our individual customers’ specifications..."

When manufacturing an accelerator that stitches together dual compute dies, multiple HBM3e/HBM4 stacks, and high-speed bridge interconnects onto TSMC’s Chip-on-Wafer-on-Substrate (CoWoS):

• Yield Risk Scrap: If one micro-bump connection fails during the 2.5D/3D integration process, an entire package consisting of thousands of dollars of prime silicon and memory dies is ruined.
• The Packaging Bridge: Broadcom manages the physical floorplanning, thermal expansion dissipation, power delivery integrity, substrate routing, and backend testing. TSMC provides the cleanroom and tooling, but Broadcom provides the design methodology, standard cell libraries, and yield engineering required to bring packaging yields to viable commercial thresholds. Alphabet does not maintain the internal armies of physical design and packaging engineers needed to perform turnkey management at this scale.

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3. System-Level Rack Architecture and Networking Lock-In

Broadcom does not sell isolated chips; it architects the holistic communications infrastructure of the datacenter rack:

• The Network Fabric: Custom compute silicon must interface seamlessly with datacenter switching fabrics. Broadcom owns the dominant merchant switching silicon (Tomahawk and Jericho lines) and enterprise PCIe switching platforms.
• Protocol Co-Optimization: Google’s internal Jupiter datacenter network fabric is tightly coupled to Broadcom's switching silicon, network interface controllers (NICs), and optical physical layer devices (PHYs). By designing both the internal accelerator's network interface and the external rack-level switches, Broadcom ensures that the TPU infrastructure communicates at theoretical maximum throughput without protocol translation bottlenecks.

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4. A Decade of Cumulative Architectural Sunk Cost

Broadcom and Google have co-developed successive TPU generations since the program's inception over a decade ago.

• Tooling and Compilers: The low-level firmware abstraction layers, hardware telemetry, power monitoring circuits, and automated testing rigs inside Google’s datacenter deployments are built specifically around Broadcom’s implementation pipeline.
• Long-Term Contractual Continuity: Commercial agreements governing TPU development between Google and Broadcom stretch through 2031. Replacing Broadcom as the primary physical architect for flagship training TPUs would require rewiring internal verification frameworks, recalibrating low-level diagnostic software, and accepting multi-quarter execution delays in the middle of an intense frontier AI deployment race.

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Where the Moat Faces Real Limits

While Broadcom’s moat on primary flagship accelerators is durable, it is not impenetrable. The primary fundamental risks include:

1. Dual-Sourcing of Ancillary Silicon: Hyperscalers actively resist single-vendor dependence. Marvell Technology’s expanding custom silicon engagements with Alphabet demonstrate that Google is actively dual-sourcing peripheral infrastructure (including inference accelerators, custom storage controllers, and memory interface silicon). While Broadcom maintains its grip on core multi-die training TPUs, high-volume lower-complexity inference silicon can be peeled away by competitors.
2. Customer Concentration and Insourcing: Alphabet is Broadcom's largest custom silicon customer. As custom programs scale from tens of thousands of chips to millions of units, the economic incentive for hyperscalers to vertically integrate physical design—or pit Broadcom against alternatives like MediaTek to force gross margin concessions—grows with every generation.

Investment Verdict

Broadcom does not need to absorb TSMC’s multi-billion-dollar capacity risk to earn exceptional economic returns (delivering a 40.8% operating margin and a 67.8% gross margin in fiscal 2025).

Its moat is protected because Alphabet is buying execution insurance and irreplaceable physical IP. Alphabet gladly takes the balance-sheet capacity risk at TSMC because it owns the end-workload demand; it pays Broadcom handsomely because failing to master high-speed SerDes, physical packaging yields, and rack-level networking would turn Alphabet's expensive TSMC wafer allocations into billions of dollars of non-functioning scrap.